1. Field of the Invention
The invention relates to improvements to circuitry used in very large scale integrated CMOS memory circuits.
2. Description of the Prior Art
An Improved Output Driver to Control Switching Noise
In U.S. Pat. No. 5,241,497 (1993), entitled "VLSI Memory with Increased Memory Access Speed, Increased Memory Cell Density and Decreased Parasitic Capacitance", a continuation of which is copending and incorporated herein by reference, an output driver was described in connection with FIGS. 14, 15, 29 and 31 in which the switching speed of the output driver was controlled with a bias circuit that compared an RC delay and gate delay. The assumption of the control assumed that the delay of the read cycle of the read-only memory (ROM) varied substantially. This variation arises due to manufacturing variables, temperature changes, and operating voltage variations. The output drivers in the ROM are designed to be as fast as a switching noise will allow for the slowest read cycle of the ROM. Therefore, for the faster read cycles, the output driver switching speed is slower than the read cycle speed and thus the switching noise is reduced.
The ROM is designed to perform with a maximum access time. In the case of ROMs which are designed to have fast read cycles, the switching speed of the output drivers may be delayed without penalty as long as the total read cycle delay is less than the maximum access time.
What is needed however is an output driver which incorporates the advantages described above, but which can be implemented in a CMOS design. The output driver switching speed should also be controlled for both rising and falling edges. In the above-mentioned NMOS version, the output driver switching speed was controlled only for the falling edge of the driver. It would further be advantageous to use the voltage precharge signal to control the output driver switching speed. Independent control of normal and slow switching speeds would be desirable. Reduction of power supply and ground voltage noise would be of benefit.
A Bias Generator for Control of Output Buffer Switching Noise.
The above-referenced copending application, now issued as U.S. Pat. No. 5,241,497, includes in connection with the description of FIGS. 25-30, the description of a circuit using both RC and gate delays to generate a bias control signal for controlling the switching speed of an output driver. However, the design described therein is adaptable only for NMOS designs, has a relatively fixed RC delay time, is somewhat subject to process variations in the chip, and has a circuit speed performance which in some scenarios can be improved.
Memory Core Supply Voltage and Bit Line Control Voltage for a CMOS ROM
Read-only memory circuits use a precharge voltage, VPC, throughout the circuit to, among other things, precharge the bit lines in the memory. The precharged voltage, VPC, is a low supply voltage supplied in the read-only memory by a power supply circuit. For example, in the above co-pending application, now issued as U.S. Pat. No. 5,241,497 the voltage VPC is generated by an NMOS circuit and has an output which varies slightly as the high supply voltage, VDD, increases. The circuit employs feedback amplifiers to reduce the recovery time when negative voltage transients occur on its output. However, the NMOS portion of the ROM is not always being accessed and therefore has a power-down mode. During the power-down mode, the ROM must operate under reduced power, typically at a maximum standby power level.
Therefore, what is needed is a circuit for generating the precharged voltage, VPC, used in a read-only memory which is adaptable to CMOS design, which is capable of powering down during the standby operation or to a lower level specified for maximum standby power supply current, but which does not sacrifice its ability to provide appropriate operating supply voltages which must be maintained even during standby operation.
An Improved NMOS Input Receiver Circuit
In a read-only memory, the memory is accessed through an address input. Switching noises from inside the read-only memory can feedback into the input receiver circuit and affect a detection of the TTL voltage input levels. This noise could change a switching level of the input receiver to result in a false address input. This would occur, for example, in the case of very slow moving and noisy inputs when the noise would be falsely detected as an address transition and a new read cycle erroneously started.
What is needed is a design for an improved input receiver for use in a read-only memory circuit which is immune from feedback noise from the read-only memory circuit.
Output Driver Control for ROM and RAM Devices
Read only memories and random access memories typically have output drivers through which the data is buffered and driven off-chip onto a bus. Typically, such output drivers are tristated, having a high logic level, low logic level and a floating or open voltage so that the connected bus lines can be set at other logic levels by other devices on the bus. However, depending upon the output driver timing, buffering problems can arise as a result of system noise, power dissipation in the output driver and in system data bus contention conflicts.
What is need is an improved output driver float timing control which is more immune to system noise, lends itself to lower power dissipation in the output driver and avoids system data bus contention conflicts.
Dynamic ROM Design for Read Cycle Interrupts
In memories which include dynamic circuits, latches, clocked logic gates and address transition detection circuits, it is possible that address skew errors can arise in which a malfunction occurs when a read cycle interrupts a memory cycle in an attempt to establish a new read cycle. In very simple prior art memories, address skew errors very rarely arise. However in more sophisticated designs having a large number of dynamic circuits, latches, address transition circuits, clocks and clocked logic gates, as is increasingly the case with larger memories, the probability of address skew becoming a significant problem substantially increases.
Therefore, what is needed is a design for controlling the timing of clocks in an interrupted cycle and a design for circuits in a memory to properly respond to these clocks in order to avoid address skew errors.
ROM Code Mask Programmable CMOS Latch
The NMOS ROM mode control circuit shown in FIG. 23 is a prior art circuit devised by the assignee of the applicant and is characterized by using two ROM core FETs, each FET denoted by reference numeral 546 and 548. The logic level of the output node 544, MDOE, is programmed high or low by controlling the threshold voltage implants for FETs 546 or 548 within circuit 540. This control provides an easy means of changing among various types of circuit operating modes in a ROM memory during the conventional encoding step in the manufacture of a VLSI memory.
The circuit of FIG. 23 also provides a means of limiting the source to drain voltage across core FETs 546 and 548. This is accomplished by a cascade connection of FET 550 and the use of a low voltage signal, GVPC, on the gate of FET 550. By this means, the voltage at node 552 is less than 3 volts. GVPC is an internal voltage supply which hi the illustrated embodiment is about 3.5 volts.
What is needed is a circuit to replace the function of that shown in FIG. 23, but which is adapted for CMOS processing. The circuit should have very low power dissipation after the power is applied and should be able to latch to the proper logic state with small differences in the threshold voltages. After the latching is completed, the data in the latch should be immune to power bus transients. The output of the latch should be at the circuit logic levels and connectable directly to logic gates within the circuit.